This invention relates to a data processing system and, more particularly, to an improved processor driven terminal structured so as to obviate the need for a direct memory access circuit and to improvements in controlling the timing of a video display.
Whereas the invention will be described in conjunction with a video display terminal capable for use as an editing terminal, as in electronic newsroom operation and the like, it is to be understood that the invention has other applications requiring the need for data processing.
At this stage in the art, a microprocessor typically comprises a central processing unit (CPU) and related circuitry mounted on a single chip; that is, a single integrated circuit. A microprocessor system includes such a central processing unit CPU, sometimes referred to as a microprocessor unit MPU, together with other circuitry including external memory. This is all connected to the CPU by a way of a bus structure which couples the CPU with external memory such as a read only memory (ROM) and a random access read/write memory (RAM). Data to be processed may be entered as by way of a tape, host computer, or by a keyboard and this data is entered by way of the bus structure to the read/write memory. The processing is typically controlled by an instruction set located in the read only memory, ROM. Data may be outputted to such output peripherals as a printer, control mechanism or a video display, including a cathode ray tube CRT. A processor driven video display terminal includes such a CPU, external memory, a keyboard and a video display. Such a processor driven video display terminal is frequently referred to as a "intelligent" video display terminal.
Intelligent terminals may be interactive with a host computer so that instruction sets as well as data may be downloaded into a random access memory. In other cases only data is downloaded and all instruction sets are preprogrammed in the read only memory ROM or they may be field variable as by a programmable read only memory PROM or by an electrically programmable read only memory, EPROM.
In these variations of processor driven systems, instructions are fetched from external memory by outputting addresses on the common bus structure. The address is a multibit binary word, typically sixteen bits. The address is typically obtained from a program counter located within the central processing unit, CPU. The term "counter" is somewhat loosely used in the art since it sometimes serves as merely an address register and receives the address of the next instruction from some other source. Frequently, the counter acts in the capacity of a counter and is periodically incremented by one count to provide the next instruction address. Sometimes the counter acts in one mode as a counter and in another mode it is forced to a particular count by loading a number into it from another source. This "number" or "count" serves as an address and is placed on the address bus of the bus structure to address the external memory (such as a read only memory) to obtain the next instruction.
The instruction so fetched determines how data stored in the data memory, such as the read/write or RAM memory, is to be processed. This data memory must also be addressed and this is done by a different addressing circuit then that employed for addressing the instructions. Frequently this data addressing circuit is known as a direct memory access (DMA) circuit. It represents one more chip in the "chipcount" needed to construct such a processing system. As the chipcount increases there is a corresponding increase in size of the processing system as well as in production time, complexity and, hence, cost of manufacture.
It is desirable, therefore, that to minimize the size of such a processing system as well as to minimize the expenses of construction, the "chipcount" should be minimized. In accordance with one aspect of the present invention this is achieved by employing the program counter of the CPU to provide the addresses for addressing the read/write memory (RAM) to obtain data for an input or output device. This, then, will obviate the need for a separate addressing circuit, such as a direct memory access circuit (DMA).
A video display terminal typically requires substantial apparatus for obtaining synchronization of operation both in the fetching of characters to be displayed and in the displaying of the characters. For example, data is obtained from a read/write memory and loaded into a temporary line buffer memory from which the data is supplied to a character generator from which dot patterns are obtained to use in generating characters on the face of a display means, such as a cathode ray tube CRT. During this operation the line buffer must be loaded with data representing characters and, once loaded, the contents must be outputted to a character generator. Additionally the outputs obtained from the character generator are applied to a character forming circuitry which, for example, may include an output shift registers. These operations must be synchronized. If the terminal be processor driven, then these various operations which require synchronization should be done in synchronization with the operation of the processor. For example, data to be retrieved from the main memory and loaded into the line buffer typically requires some operation by the CPU in conjunction with a direct memory access circuit. This operation must be synchronized so as to not interrupt other data processing operations and so as to not take place during video display time. Typically, substantial counter circuitry is required to synchronize these various operations. Additionally, the operations are usually synchronized to a line frequency signal or to a synchronization signal provided by a TV monitor circuit.
One aspect of the present invention deals with simplifying the circuitry employed to achieve video control and timing in a video display terminal. This is achieved with a more simplified circuitry which provides sequence control. Preferably, the sequence controller includes a microcomputer which operates to provide the required synchronization and timing signals.